Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for an SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology scaling, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 /spl mu/m and below.
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机译：静态随机存取存储器（SRAM）的延迟，功耗和面积的简单模型用于确定SRAM的最佳组织，并研究其速度和功耗随大小和技术的缩放比例。发现每增加1 Mb的RAM大小，每增加一倍，该延迟就会增加大约一个门延迟，超过此延迟，互连延迟将占总延迟的比例越来越大。通过技术缩放，发现感应放大器中阈值失配的非缩放会严重影响0.1 / spl mu / m或以下的总延迟。
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