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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals
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A 1.8-mW CMOS ΣΔ modulator with integrated mixer forA/D conversion of IF signals

机译:具有集成混频器的1.8mW CMOSΣΔ调制器,用于IF信号的A / D转换

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In this paper, the design of a continuous-time basebandnsigma-delta (ΣΔ) modulator with an integrated mixer fornintermediate-frequency (IF) analog-to-digital conversion is presented.nThis highly linear IF ΣΔ modulator digitizes a GSM channelnat intermediate frequencies up to 50 MHz. The sampling rate is notnrelated to the input IF and is 13.0 MHz in this design. Powernconsumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82ndB, and third-order intermodulation distortion is -84 dB for two -6-dBVnIF input tones. Two modulators in quadrature configuration providen200-kHz GSM bandwidth. Active area of a single IF ΣΔnmodulator is 0.2 mm2 in 0.35-Μm CMOS
机译:本文介绍了一种具有集成混频器的连续时间基带Σ-Δ调制器的设计,用于中频(IF)模数转换.n这种高度线性的IFΣΔ调制器将GSM信道中频向上数字化到50 MHz采样速率与输入IF无关,在本设计中为​​13.0 MHz。 2.5V电源的功耗为1.8 mW。测得的动态范围为82ndB,并且对于两个-6-dBVnIF输入音,三阶互调失真为-84 dB。两个正交配置的调制器提供200kHz的GSM带宽。在0.35-μmCMOS中,单个IFΣΔn调制器的有效面积为0.2 mm2

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