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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An ultra low power adaptive wavelet video encoder with integrated memory
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An ultra low power adaptive wavelet video encoder with integrated memory

机译：具有集成存储器的超低功耗自适应小波视频编码器

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This paper describes a low-power, single-chip video encoder intended for battery-operated portable applications. Design goals are minimizing system power as well as utilized bandwidth, and maximizing system integration. The encoder achieves competitive compression, with convenient bit rate scalability, using a peak power dissipation of several hundred /spl mu/W on a video stream of 8-bit gray scale, 30 frame/s, and 128/spl times/128 demonstration resolution. Compression is performed using wavelet filtering, zero-trees, and arithmetic coding, all integrated on a single chip (3 million transistors, 1 cm/sup 2/, in 0.6 /spl mu/m CMOS, operating at 500 kHz), with no external memory or control. Results do not include use of motion compensation, however, hooks are included at algorithmic and architectural levels to add motion compensation at the cost of power dissipation a few times higher, and more internal memory. In the absence of motion compensation, temporal correlation is still utilized through the use of simple frame differencing. The architectural centerpiece is a massively parallel, fine granularity SIMD array of processing elements (PEs). A mapping is made between small image blocks (4/spl times/4 pixels on the test chip) and PEs, with each PE containing both memory and logic required for its block. These results are obtained by careful coordination of design in a deep vertical manner, ranging from system, algorithmic, architectural, circuit, and layout, and designing simultaneously for all required algorithmic subcomponents.
机译：本文介绍了一种用于电池供电的便携式应用的低功耗单芯片视频编码器。设计目标是最大程度地降低系统功耗和带宽利用率，并最大程度地提高系统集成度。该编码器在8位灰度级，30帧/秒和128 / spl次/ 128演示分辨率的视频流上使用数百/ spl mu / W的峰值功耗，从而实现了具有竞争力的压缩和便利的比特率可扩展性。 。使用小波滤波，零树和算术编码执行压缩，所有压缩均集成在单个芯片上（300万个晶体管，1 cm / sup 2 /，0.6 / spl mu / m CMOS，工作于500 kHz）外部存储器或控件。结果不包括运动补偿的使用，但是，在算法和体系结构级别都包含了挂钩，以增加运动补偿的代价增加了几倍的功耗，并增加了内部内存。在没有运动补偿的情况下，仍然通过使用简单的帧差分来利用时间相关性。该架构的核心是一个大规模并行，细粒度的SIMD处理元件（PE）阵列。在小图像块（测试芯片上为4 / spl乘以4像素）与PE之间进行映射，每个PE都包含其块所需的存储器和逻辑。这些结果是通过在系统，算法，体系结构，电路和布局等各方面的深度垂直方式下精心设计协调并同时为所有必需的算法子组件进行设计而获得的。

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