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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A family of low-power truly modular programmable dividers instandard 0.35-Μm CMOS technology
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A family of low-power truly modular programmable dividers instandard 0.35-Μm CMOS technology

机译:采用标准0.35-μmCMOS技术的低功耗真正模块化可编程分频器系列

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摘要

A truly modular and power-scalable architecture for low-powernprogrammable frequency dividers is presented. The architecture was usednin the realization of a family of low-power fully programmable dividerncircuits, which consists of a 17-bit UHF divider, an 18-bit L-bandndivider, and a 12-bit reference divider. Key circuits of thenarchitecture are 2/3 divider cells, which share the same logic and thensame circuit implementation. The current consumption of each cell can bendetermined with a simple power optimization procedure. Thenimplementation of the 2/3 divider cells is presented, the powernoptimization procedure is described, and the input amplifiers arenbriefly discussed. The circuits were processed in a standard 0.35 Μmnbulk CMOS technology, and work with a nominal supply voltage of 2.2 V.nThe power efficiency of the UHF divider is 0.77 GHz/mW, and of thenL-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mVnrms for the UHF divider, and >20 mV rms for the L-band divider
机译:提出了一种用于低功耗可编程分频器的真正模块化且可扩展功率的架构。该体系结构用于实现低功耗完全可编程分频器系列,该电路由一个17位的UHF分频器,一个18位的L带分频器和一个12位的参考分频器组成。该架构的关键电路是2/3分频器单元,它们共享相同的逻辑,然后实现相同的电路实现。每个电池的电流消耗可以通过简单的功率优化程序确定。然后介绍了2/3分频器单元的实现,描述了功率优化过程,并简要讨论了输入放大器。这些电路采用标准的0.35 Mmnbulk CMOS技术进行处理,并在2.2 V的标称电源电压下工作。nUHF分频器的功率效率为0.77 GHz / mW,L频段分频器的功率效率为0.57 GHz / mW。对于UHF分频器,测得的输入灵敏度为> 10 mVnrms,对于L波段分频器,则为> 20 mV rms

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