1-GHz fully pipelined 3.7-ns address access time 8 k×1024embedded synchronous DRAM macro

Takahashi O.; Dhong S.H.; Ohkubo M.; Onishi S.; Dennard R.H.; Hannon R.; Crowder S.; Iyer S.S.; Wordeman M.R.; Davari B.; Weinberger W.B.; Aoki N.

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1-GHz fully pipelined 3.7-ns address access time 8 k×1024embedded synchronous DRAM macro

机译：1 GHz全流水线3.7ns地址访问时间8 k×1024嵌入式同步DRAM宏

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This embedded-DRAM macro is designed as a DRAM cache for a futurengigahertz microprocessor system based on a logic-based DRAM technology.nThe most notable feature of this macro is its ability to runnsynchronously with a gigahertz CPU clock in a fully pipelined fashion.nIt is designed to operate with a 1-GHz clock signal at 85°C, nominalnprocess parameters, and a 10% degraded VDD. The design isnfully pipelined and synchronous with 16 independent subarrays. With 1-kbnwide I/0 and a 1-GHz clock, the maximum data rate becomes 1 Tb pernsecond. The address access time is 3.7 ns, four cycles with a 1-GHznclock. The subarray cycle time is 12 ns

机译：这个嵌入式DRAM宏被设计为基于逻辑DRAM技术的未来千兆赫微处理器系统的DRAM缓存。n该宏的最显着特征是它能够以完全流水线的方式与千兆赫CPU时钟同步运行。设计用于在85°C的1-GHz时钟信号，标称工艺参数和VDD降低10％的条件下工作。该设计完全流水线化，并与16个独立的子阵列同步。使用1kbnwide I / 0和1GHz时钟，最大数据速率为每秒1 Tb。地址访问时间为3.7 ns，一个1 GHz时钟为四个周期。子阵列周期时间为12 ns

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《IEEE Journal of Solid-State Circuits》 |2000年第11期|p.1673-1679|共7页
作者
Takahashi O.; Dhong S.H.; Ohkubo M.; Onishi S.; Dennard R.H.; Hannon R.; Crowder S.; Iyer S.S.; Wordeman M.R.; Davari B.; Weinberger W.B.; Aoki N.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
DRAM chips; cache storage; cellular arrays; embedded systems; parallel memories; pipeline processing; 1 GHz; 12 ns; 3.7 ns; 85 degC; DRAM cache; address access time; data rate; embedded synchronous DRAM macro; fully pipelined fashion; gigahertz microprocessor system; in;

机译：DRAM芯片;高速缓存存储;单元阵列;嵌入式系统;并行存储器;管道处理;1 GHz;12 ns;3.7 ns;85 degC;DRAM高速缓存;地址访问时间;数据速率;嵌入式同步DRAM宏;完全流水线方式;千兆赫兹微处理器系统;

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1. 1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro [J] . Takahashi O., Dhong S.H. IEEE Journal of Solid-State Circuits . 2000,第11期

机译：1-GHz全流水线3.7ns地址访问时间8k / spl次/ 1024个嵌入式同步DRAM宏
2. A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time andmemory-cell area efficiency of 33% [J] . Yokoyama Y., Itoh N., Hasegawa M., IEEE Journal of Solid-State Circuits . 2001,第3期

机译：一个1.8V嵌入式18Mb DRAM宏，具有9ns的RAS访问时间，存储单元面积效率为33％
3. A 500-MHz Multi-Banked Compilable DRAM Macro With Direct Write and Programmable Pipelining [J] . John E. Barth Jr., Darren Anand, Steve Burns, IEEE Journal of Solid-State Circuits . 2005,第1期

机译：具有直接写入和可编程流水线功能的500 MHz多存储区可编译DRAM宏
4. 1 GHz fully pipelined 3.7 ns address access time 8 k/spl times/1024 embedded DRAM macro [C] . Takahashi, O., Dhong, . 2000

机译：1 GHz全流水线3.7 ns地址访问时间8 k / spl次/ 1024个嵌入式DRAM宏
5. Scan synchronous directional antennas for time division multiple access in multi-hop ad hoc wireless networks. [D] . Charbonneau, Terrance Wayne. 2005

机译：在多跳自组织无线网络中扫描同步定向天线以进行时分多址访问。
6. Flucytosine and cryptococcosis: time to urgently address the worldwide accessibility of a 50-year-old antifungal [O] . Angela Loyse, Françoise Dromer, Jeremy Day, -1

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7. Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design [O] . Rémi Parrot, Mikaël Briday, Olivier H. Roux 2021

机译：定时培养网重置流水线同步电路设计
8. FINAL REPORT PARAMETERS OF A NON-SYNCHRONOUS, RANDOM ACCESS, DISCRETE ADDRESS COMMUNICATIONS SYSTEM [R] . Leo R. Spogen, William H. Reading, Victor R. Larorre 1961

机译：非同步，随机接入，离散地址通信系统的最终报告参数

1-GHz fully pipelined 3.7-ns address access time 8 k×1024embedded synchronous DRAM macro

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