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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSIchip using low-power bipolar-LSI design
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A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSIchip using low-power bipolar-LSI design

机译:采用低功耗双极LSI设计的557mW,2.5Gbit / s SONET / SDH再生器端接LSI芯片

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摘要

A regenerator-section terminating digital large-scale-integrationnchip for an STM-16 (2.5-Gbit/s synchronous optical network/synchronousndigital hierarchy) regenerator has been developed using low-powernbipolar technologies. The high-speed performance of bipolar devicesnenabled four or more chips, including a demultiplexer and a multiplexer,nto be integrated into a single chip. The low-power dissipation of 557nmW, only about one-tenth that of previously reported chips, was achievednthrough the use of four design steps: one-chip integration architecture,npower management, 2.5-V emitter-coupled logic, and power optimization
机译:已经使用低功率双极技术开发了用于STM-16(2.5-Gbit / s同步光网络/同步数字层次)再生器的再生器部分终端数字大规模集成芯片。双极型器件的高速性能可以将包括解复用器和复用器的四个或更多芯片集成到单个芯片中。 557nmW的低功耗仅为以前报告的芯片的十分之一,这是通过以下四个设计步骤实现的:单芯片集成架构,n电源管理,2.5 V发射极耦合逻辑以及功耗优化

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