A low-jitter PLL clock generator for microprocessors with lockrange of 340-612 MHz

Boerstler D.W.

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A low-jitter PLL clock generator for microprocessors with lockrange of 340-612 MHz

机译：用于微处理器的低抖动PLL时钟发生器，锁定范围为340-612 MHz

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A fully integrated, phase-locked loop (PLL) clock generator/phasenaligner for the POWER3 microprocessor has been designed using a 2.5-V,n0.40-Μm digital CMOS6S process. The PLL design supports multipleninteger and noninteger frequency multiplication factors for both thenprocessor clock and an L2 cache clock. The fully differentialndelay-interpolating voltage-controlled oscillator (VCO) is tunable overna frequency range determined by programmable frequency limit settings,nenhancing yield and application flexibility. PLL lock range for thenmaximum VCO frequency range settings is 340-612 MHz. The charge-pumpncurrent is programmable for additional control of the PLL loop dynamics.nA differential on-chip loop filter with common-mode correction improvesnnoise rejection. Cycle-cycle jitter measurements with the microprocessornactively executing instructions were 10.0 ps rms, 80 ps peak to peakn(P-P) measured from the clock tree. Cycle-cycle jitter measured for thenprocessor in a reset state with the clock tree active was 8.4 ps rms, 62nps P-P. PLL area is 1040×640 Μm2. Power dissipationnis <100 mW

机译：已使用2.5V，n0.40μm数字CMOS6S工艺设计了用于POWER3微处理器的完全集成的锁相环（PLL）时钟发生器/相位对准器。 PLL设计支持随后处理器时钟和L2高速缓存时钟的倍数和倍数倍频系数。全差分延迟内插压控振荡器（VCO）可在整个频率范围内进行可调，该频率范围由可编程频率限制设置确定，从而提高了产量和应用灵活性。然后，最大VCO频率范围设置的PLL锁定范围为340-612 MHz。电荷泵电流是可编程的，可以进一步控制PLL环路动态。具有共模校正的差分片上环路滤波器可改善噪声抑制性能。微处理器主动执行指令的周期抖动测量为10.0 ps rms，从时钟树测得的峰峰值为80 ps（P-P）。在时钟树处于活动状态的复位状态下，为处理器测得的周期抖动为8.4 ps rms，62nps P-P。 PLL面积为1040×640μm2。功耗nis <100 mW

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来源
《IEEE Journal of Solid-State Circuits》 |1999年第4期|p.513-519|共7页
作者
Boerstler D.W.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS digital integrated circuits; clocks; digital phase locked loops; microprocessor chips; timing jitter; voltage-controlled oscillators; 0.40 micron; 100 mW; 2.5 V; 340 to 612 MHz; L2 cache; PLL clock generator; POWER3 microprocessor; common-mode correction; cycle-c;

机译：CMOS数字集成电路;时钟;数字锁相环;微处理器芯片;时序抖动;压控振荡器;0.40微米;100 mW;2.5 V;340至612 MHz;L2高速缓存;PLL时钟发生器;POWER3微处理器;共模校正;循环;

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专利

1. A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz [J] . Boerstler D.W. IEEE Journal of Solid-State Circuits . 1999,第4期

机译：低抖动PLL时钟发生器，用于锁定范围为340-612 MHz的微处理器
2. A PLL clock generator with 5 to 10 MHz of lock range for microprocessors [J] . Young I.A., Greason J.K. IEEE Journal of Solid-State Circuits . 1992,第11期

机译：锁定范围为5到10 MHz的PLL时钟发生器
3. Design of Fully Integrated Programmable PLL Frequency Synthesizers for Microprocessor Clocking at 1-1500 MHz [J] . V. D. Baikov, A. A. Garmash, Yu. B. Rogatkin, Russian Microelectronics . 2007,第2期

机译：用于1-1500 MHz微处理器时钟的全集成可编程PLL频率合成器的设计
4. Low-power low-jitter PLL clock synthesizer for microprocessors with clock range 200-768 MHz [C] . V Baykov, A Garmash International Telecommunication Conference on Advanced Micro- and Nanoelectronic Systems and Technologies . 2015

机译：低功耗低抖动PLL时钟合成器，微处理器的时钟范围为200-768 MHz
5. Low-jitter PLL for clock generator with supply-noise-insensitive VCO using DC-DC capacitive converter. [D] . Lee, Chang-Hyeon. 1999

机译：用于时钟发生器的低抖动PLL，具有使用DC-DC电容转换器的对电源噪声不敏感的VCO。
6. Modeling the Nucleus Laminaris of the Barn Owl: Achieving 20 ps Resolution on a 85-MHz-Clocked Digital Device [O] . Ralf Salomon, Enrico Heinrich, Ralf Joost 2012

机译：建模谷仓猫头鹰的椎板中层：在85MHz时钟数字设备上实现20µps的分辨率
7. A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors [O] . Ian A. Young, Jeffrey K. Greason, Keng L. Wong 1992

机译：pLL时钟发生器，具有5至110 mHz的微处理器锁定范围

A low-jitter PLL clock generator for microprocessors with lockrange of 340-612 MHz

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