Comparative analysis of master-slave latches and flip-flops forhigh-performance and low-power systems

Stojanovic V.; Oklobdzija V.G.

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Comparative analysis of master-slave latches and flip-flops forhigh-performance and low-power systems

机译：高性能和低功耗系统的主从锁存器和触发器的比较分析

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In this paper, we propose a set of rules for consistent estimationnof the real performance and power features of the flip-flop andnmaster-slave latch structures. A new simulation and optimizationnapproach is presented, targeting both high-performance and power budgetnissues. The analysis approach reveals the sources of performance andnpower-consumption bottlenecks in different design styles. Certainnmisleading parameters have been properly modified and weighted tonreflect the real properties of the compared structures. Furthermore, thenresults of the comparison of representative master-slave latches andnflip-flops illustrate the advantages of our approach and the suitabilitynof different design styles for high-performance and low-powernapplications

机译：在本文中，我们提出了一套规则，用于对触发器和主从锁存器结构的实际性能和功率特性进行一致的估计。提出了针对高性能和功耗预算问题的新仿真和优化方法。分析方法揭示了不同设计风格下性能和功耗瓶颈的根源。对某些误导性参数进行了适当修改，加权加权反映了所比较结构的真实属性。此外，代表性的主从锁存器和触发器的比较结果说明了我们的方法的优势以及不同设计风格对高性能和低功耗应用的适用性

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来源
《IEEE Journal of Solid-State Circuits》 |1999年第4期|p.536-548|共13页
作者
Stojanovic V.; Oklobdzija V.G.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
flip-flops; integrated circuit design; low-power electronics; sequential circuits; consistent estimation; design styles; low-power systems; master-slave latches; power budget issues;

机译：触发器;集成电路设计;低功耗电子设备;时序电路;一致的估计;设计风格;低功耗系统;主从锁存器;功率预算问题;

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专利

1. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems [J] . Stojanovic V., Oklobdzija V.G. IEEE Journal of Solid-State Circuits . 1999,第4期

机译：高性能和低功耗系统的主从锁存器和触发器的比较分析
2. A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops [J] . Wai Chung, Lo T., Sachdev M. IEEE transactions on very large scale integration (VLSI) systems . 2002,第6期

机译：低功耗低压双沿触发触发器的比较分析
3. A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops [J] . Wai Chung, Lo T., Sachdev M. IEEE transactions on very large scale integration (VLSI) systems . 2002,第6期

机译：低功耗低压双沿触发触发器的比较分析
4. Comparative analysis and design of harmonic aware low-power latches and flip-flops [C] . Khan Muhammad Imran, Fujiang Lin IEEE International Conference on Electron Devices and Solid-State Circuits . 2014

机译：谐波感知型低功耗锁存器和触发器的比较分析和设计
5. Exploiting Master-Slave Bus Architecture and Storage Devices to Enable High-Performance, Low-Power Logging for Sensor Systems. [D] . Yoon, Eunbae. 2013

机译：利用主从总线架构和存储设备来为传感器系统实现高性能，低功耗的日志记录。
6. A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product [O] . Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta -1

机译：基于三态逆变器的静态主从触发器的改进实现具有改进的功率延迟面积积
7. Comparative study on low-power high-performance standard-cell flip-flops [O] . S. Tahmasbi Oskuii, A. Alv 2008

机译：低功耗高性能标准单元触发器的比较研究

Comparative analysis of master-slave latches and flip-flops forhigh-performance and low-power systems

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