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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 450-Mb/s analog front end for PRML read channels
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A 450-Mb/s analog front end for PRML read channels

机译:用于PRML读取通道的450 Mb / s模拟前端

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摘要

A 450-Mbit/s analog front end, integrated into a 16/17 code ratenEPR4 read channel for hard disk drives, uses an automatic gain controln(AGC) circuit with digital feedback. Multilevel qualification and anvariable loop time constant enable the AGC to acquire a 12-dB gainnchange within 5 data bytes. The front-end circuitry incorporates anprogrammable gain amplifier (PGA), an exponential variable gainnmultiplier (VGA), a seventh-order 0.05° equiripple linear phasen20-120-MHz low-pass filter with 0-15-dB high-frequency boost, and activenac coupling. The PGA and VCA combine to give a 48-dB gain range with an500 MHz -1-dB bandwidth for a power supply of 3 V. The embodiment ofnthermal asperity and amplitude asymmetry compensation circuitry makesnthe analog front end ideally suited for applications usingnmagnetoresistive read heads. Implemented in a 5-/3.3-V dual-voltagen.35-Μm BiCMOS process with a gate-oxide thickness of 75 nm and 16-GHznnpn FT, the complete circuit occupies 2.29 mm2 andndissipates 232 mW
机译:集成到硬盘驱动器的16/17码率nEPR4读取通道中的450 Mbit / s模拟前端使用带有数字反馈的自动增益控制(AGC)电路。多级限定和可变的循环时间常数使AGC能够在5个数据字节内获得12 dB的增益变化。前端电路包括一个可编程增益放大器(PGA),一个指数可变增益倍增器(VGA),一个7阶0.05°等波纹线性相位n20-120MHz低通滤波器,具有0-15dB的高频升压功能,以及有源耦合。 PGA和VCA结合在一起,可为3 V电源提供48 dB的增益范围和500 MHz -1- dB的带宽。非均一性和幅度不对称补偿电路的实施方案使该模拟前端非常适合使用磁阻式读取头的应用。完整的电路采用5- / 3.3V双电压,n.35μmBiCMOS工艺实现,栅氧化层厚度为75nm,FT-16-GHznnpn,总面积为2.29mm2,功耗为232mW。

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