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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A single-chip universal digital satellite receiver with 480-MHz IFinput
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A single-chip universal digital satellite receiver with 480-MHz IFinput

机译:具有480MHz IF输入的单芯片通用数字卫星接收器

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This paper presents a complete single-chip universal digitalnsatellite receiver supporting all current DBS system standards. Thenmixed-signal device accepts a modulated data stream at up to 90 Mbps andndelivers a demodulated, error-corrected output data stream. The ICnfeatures an analog front end with 480-MHz intermediate frequencyndownconversion and dual 8-bit analog-to-digital converters, annall-digital BPSK/QPSK/OQPSK variable-rate receiver supporting 1-45 MBaudnoperation with phase/frequency recovery, variable-rate digital filters,nsquare-root Nyquist matched filters, acquisition and tracking loops, andna DVB/DSS/DigiCipher I/II-compliant concatenated Viterbi/Reed-Solomonnforward error correction decoder with on-chip deinterleaver RAM. Allnrequired clocks are generated on chip from a single reference crystal.nThe chip contains 1.2 million transistors in a die area of 22 mm2n and was implemented in a single-poly 0.35-Μm CMOS process withnfour layers of metal
机译:本文提出了一个完整的单芯片通用数字卫星接收机,它支持所有当前的DBS系统标准。然后,混合信号设备接受高达90 Mbps的调制数据流,并提供经过解调,纠错的输出数据流。该IC具有模拟前端和480MHz中频下变频,双8位模数转换器,Annal-数字BPSK / QPSK / OQPSK可变速率接收器,支持1-45 MB音频操作,具有相/频率恢复功能,可变速率数字滤波器,平方根Nyquist匹配滤波器,采集和跟踪环路,以及符合DVB / DSS / DigiCipher I / II的级联Viterbi / Reed-Solomonnforward纠错解码器,带有片上解交织器RAM。所有所需的时钟均由单个参考晶体在芯片上生成。n该芯片在22 mm2n的管芯面积中包含120万个晶体管,并通过单层0.35-μmCMOS工艺实现,具有四层金属

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