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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver
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A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver

机译：用于多比特率DSL收发器的25 kft，768 kbps CMOS模拟前端

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摘要

A transceiver for multibit-rate digital subscriber loop is presented with up to 25-kft reach on using AWG 24 wire. An adjustable data rate from 160 to 768 kb/s is employed to achieve N/spl times/64 kb/s voice channel (N=2-12). The IC contains a 14-bit, 63 dual current sources multibit /spl Sigma//spl Delta/ digital-to-analog converter with "hopping" dynamic elements, a /spl Sigma//spl Delta/ analog-to-digital converter (ADC), and an on-chip high-swing nested Miller line driver; and for full duplex communication an integrated -30 dB rejection hybrid filter based on line and transformer parasitics matching. The concept has been tested using two sets of silicon test chips, one for symmetrical digital subscriber line (SDSL) and one for asymmetrical DSL (ADSL), on a line emulator with and without additive line noise for SDSL and ADSL rates (line driver external for ADSL with fourth-order multibit ADC for ADSL). In the analog front end, supply is 3 V for all the digital blocks, including the interface to the digital portion of the DSL, and 5 V for all the analog blocks. Power is 250 mW, with 12-mm/sup 2/ area. The transceiver can cover the full set of ANSI T1.601 basic rate ISDN (UkO-interface) loops while providing 2.5 times the throughput of existing U-interface transceivers. Nearly five times the throughput (768 kb/s) can be achieved even in the presence of worst case self-crosstalk. The additional performance is achieved by using a combination of coding, digital, and analog techniques.
机译：提出了一种用于多比特率数字用户环路的收发器，使用AWG 24线时可达25 kft的传输距离。采用160到768 kb / s的可调数据速率来实现N / spl次/ 64 kb / s语音通道（N = 2-12）。该IC包含一个带“跳跃”动态元件的14位，63个双电流源多位/ spl Sigma // spl Delta /数模转换器，一个/ spl Sigma // spl Delta /模数转换器（ ADC）和片上高摆幅嵌套米勒线驱动器;对于全双工通信，基于线路和变压器寄生匹配的集成-30 dB抑制混合滤波器。该概念已使用两套硅测试芯片进行了测试，一套用于对称数字用户线（SDSL），另一套用于非对称DSL（ADSL），在具有和不具有针对SDSL和ADSL速率的附加线路噪声的线路仿真器上（外部线路驱动器） （用于ADSL的四阶多位ADC）。在模拟前端中，所有数字模块（包括与DSL数字部分的接口）的电源为3 V，所有模拟模块的电源为5V。功率为250 mW，面积为12mm / sup 2 /。该收发器可以覆盖全套ANSI T1.601基本速率ISDN（UkO接口）环路，同时提供的吞吐量是现有U接口收发器的2.5倍。即使存在最坏情况下的自串扰，吞吐量也可以达到近五倍（768 kb / s）。通过结合使用编码，数字和模拟技术，可以实现额外的性能。

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