This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-/spl mu/m CMOS process with a die area of only 140/spl times/100 /spl mu/m/sup 2/. Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns.
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机译：本文提出了一种高速，小面积电路，专门设计用于在闪存多级存储器的读取操作中识别电平。该电路基于从存储单元读取的电流与代表不同逻辑电平的参考电流之间的欧几里德距离的模拟计算。该电路的实验版本已集成到标准双金属0.7- / spl mu / m CMOS工艺中，管芯面积仅为140 / spl乘以100 / spl mu / m / sup 2 /。该电路在5V电源下工作，可识别存储单元的读出电流，并在9 ns内将其与适当的逻辑电平关联。
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