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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A novel power-off mode for a battery-backup DRAM
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A novel power-off mode for a battery-backup DRAM

机译:电池备用DRAM的新型断电模式

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This paper proposes a new DRAM power-off mode, in which the power source is completely shut off during the standby cycle, resulting in a zero standby leakage current. By introducing a new word-line power-off/on sequence and a grounded cell plate technique, all cell data are maintained after power source is turned off and on. Although the proposed mode requires a power-on current, an average standby leakage current is reduced by a factor of 1000, and the total standby current including both the leakage current and refresh current is reduced by a factor of 10 in a 1 Gb DRAM. The proposed circuit technique was verified by a 64 Kb DRAM test chip. All cell data were successfully maintained after the power source switching. The measured power-off time was as long as the measured data retention time in the conventional DRAM standby mode.
机译:本文提出了一种新的DRAM关机模式,该模式下,在待机周期内电源完全关闭,从而使待机泄漏电流为零。通过引入新的字线断电/通电序列和接地的单元板技术,可以在电源关闭和打开后保留所有单元数据。尽管提出的模式需要上电电流,但是在1 Gb DRAM中,平均待机泄漏电流减少了1000倍,包括泄漏电流和刷新电流的总待机电流减少了10倍。所提出的电路技术已通过64 Kb DRAM测试芯片进行了验证。电源切换后,所有单元数据均已成功维护。在常规DRAM待机模式下,测得的断电时间与测得的数据保留时间一样长。

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