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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A fast parallel squarer based on divide-and-conquer
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A fast parallel squarer based on divide-and-conquer

机译:基于分治法的快速并行平方器

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摘要

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-/spl mu/m CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation.
机译:在许多应用中,例如图像压缩,需要快速而小的平方器。报告了基于分而治之方法的高性能并行平方器的新家族。我们的主要结果是通过使用优化的n位原始平方器实现分治式递归的基本情况,其中n在2到6的范围内。这种方法减少了门数并提供了较短的关键路径。设计,制造并成功测试了实现8-b平方器的芯片,使用2- / spl mu / m CMOS制造技术实现了每秒2400万次操作(MOPS)。该平方器具有两个附加功能:增加每单位电路面积的平方运算次数,并有可能降低每次平方运算的功耗。

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