To achieve unlimited concurrency and hence throughput in an area-efficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm. The SBVD approach reduces decode of a continuous input stream to decode of independent overlapping blocks, without constraining the encoding process. A systolic SBVD architecture is presented that combines forward and backward processing of the block interval. The architecture is demonstrated in a four-state, R=1/2, eight-level soft decision Viterbi decoder that has been designed and fabricated in double-metal CMOS. The 9.21 mm/spl times/8.77 mm chip containing 150 k transistors is fully functional at a clock rate of 83 MHz and dissipates 3.0 W under typical operating conditions (V/sub DD/=5.0 V, T/sub A/=27/spl deg/C). This corresponds to a block decode rate of 83 MHz, equivalent to a decode rate of 1 Gb/s. For low-power operation, typical parts are fully functional at a clock rate of greater than 12 MHz, equivalent to a decode rate of 144 Mb/s, and dissipate 24 mW at V/sub DD/=1.5 V, demonstrating extremely low power consumption at such high rates.
展开▼
机译：为了以区域有效的方式实现无限制的并发并因此获得吞吐量，实现了一种滑动块维特比解码器（SBVD），该组合将滑动块解码器的滤波特性与维特比算法的计算效率相结合。 SBVD方法减少了对连续输入流的解码，以对独立的重叠块进行解码，而不会限制编码过程。提出了一种收缩式SBVD架构，该架构结合了对块间隔的正向和反向处理。在四态，R = 1/2的八级软判决维特比解码器中演示了该架构，该解码器已在双金属CMOS中设计和制造。包含150 k晶体管的9.21 mm / spl乘以8.77 mm的芯片以83 MHz的时钟速率完全工作，在典型的工作条件下（V / sub DD / = 5.0 V，T / sub A / = 27 / spl摄氏度/度）。这对应于83 MHz的块解码速率，相当于1 Gb / s的解码速率。对于低功耗操作，典型部件以高于12 MHz的时钟速率完全工作，相当于144 Mb / s的解码速率，并且在V / sub DD / = 1.5 V时耗散24 mW，这表明功率非常低如此高的消费率。
展开▼
