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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An ATM routing and concentration chip for a scalable multicast ATM switch
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An ATM routing and concentration chip for a scalable multicast ATM switch

机译：用于可扩展的多播ATM交换机的ATM路由和集中芯片

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We have proposed a new architecture for building a scalable multicast ATM switch from a few tens to a few thousands of input/output ports. The switch, called the Abacus switch, employs input and output buffering schemes. Cell replication, cell routing, and output contention resolution are all performed in a distributed way so that the switch can be scaled up to a large size. The Abacus switch adopts a novel algorithm to resolve the contention of both multicast and unicast cells destined for the same output port (or output module). The switch can also handle multiple priority traffic by routing cells according to their priority levels. This paper describes a key ASIC chip for building the Abacus switch. The chip, called the ATM routing and concentration (ARC) chip, contains a two-dimensional array (3/spl times/32) of switch elements that are arranged in a cross-bar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8-/spl mu/m CMOS technology and tested to operate correctly at 240 MHz, Although the ARC chip was designed to handle the line rate at OC-3 (155 Mb/s), the Abacus switch can accommodate a much higher line rate at OC-12 (622 Mb/s) or OC-48 (2.5 Gb/s) by using a bit-sliced technique or distributing cells in a cyclic order to different inputs of the ARC chip. When the latter scheme is used, the cell sequence is retained at the output of the Abacus switch.
机译：我们提出了一种新的体系结构，用于构建可扩展的多播ATM交换机，该交换机从几十个输入端口到数千个输入/输出端口。该开关称为Abacus开关，采用输入和输出缓冲方案。信元复制，信元路由和输出争用解决方案均以分布式方式执行，因此交换机可以按比例放大到较大尺寸。算盘交换机采用一种新颖的算法来解决发往同一输出端口（或输出模块）的多播和单播单元的争用。交换机还可以通过根据信元的优先级来路由多个优先级流量。本文描述了构建Abacus交换机的关键ASIC芯片。该芯片称为ATM路由和集中（ARC）芯片，包含交换元件的二维阵列（3 / spl倍/ 32），它们以交叉开关结构排列。它提供了将芯片配置为不同组大小以适应不同ATM交换机大小的灵活性。 ARC芯片是使用0.8- / spl mu / m CMOS技术设计和制造的，并经过测试可在240 MHz下正确运行。尽管ARC芯片被设计为可处理OC-3（155 Mb / s）的线速，但通过使用位切片技术或以循环顺序将信元循环分配到ARC芯片的不同输入，算盘开关可以在OC-12（622 Mb / s）或OC-48（2.5 Gb / s）上提供更高的线速。使用后一种方案时，单元格序列将保留在算盘开关的输出处。

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