An on-wafer built-in self-test (BIST) technique has been developed to implement a 200 Gb/s failed-bit search for a 1-Gb DRAM. The BIST circuits include a 4-kb very-long word bus and an on-wafer test management unit to probe DRAM arrays and compress test results. The 1-Gb DRAM is fabricated as a test device using a 0.16-/spl mu/m CMOS technology. As a result, the BIST reduces the wafer test time to less than 1/100 that of bit-by-bit testing.
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机译：已经开发了晶圆内置自测（BIST）技术，以实现对1 Gb DRAM的200 Gb / s失败位搜索。 BIST电路包括一个4 KB的超长字总线和一个晶圆上测试管理单元，用于探测DRAM阵列并压缩测试结果。使用0.16- / spl mu / m CMOS技术将1-Gb DRAM制成测试设备。结果，BIST将晶片测试时间减少到少于逐位测试时间的1/100。
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