A 12-b, 60-MSample/s cascaded folding and interpolating ADC

Vorenkamp P.; Roovers R.

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A 12-b, 60-MSample/s cascaded folding and interpolating ADC

机译：一个12b，60MSample / s级联折叠和内插ADC

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This paper describes the analysis, design, and experimental results of a 12-b, 60-MSample/s analog-to-digital converter (ADC). This ADC is based on a cascaded folding and interpolating architecture. The ADC is optimized for digital telecommunication applications. The cascaded folding and interpolating ADC architecture is introduced, optimizing the overall performance of this converter. The integrated track and hold amplifier enables an SNR<66 dB and a THD>72 dB, measured over an analog input signal bandwidth of 70 MHz. The ADC is realized in a 13-GHz, 1-/spl mu/m BiCMOS process and measures 7 mm/sup 2/, while dissipating 300 mW from a single 5.0 V supply.

机译：本文介绍了12b，60MSample / s模数转换器（ADC）的分析，设计和实验结果。该ADC基于级联的折叠和内插架构。 ADC针对数字电信应用进行了优化。引入了级联折叠和内插ADC架构，优化了该转换器的整体性能。集成的采样保持放大器可在70 MHz的模拟输入信号带宽上实现SNR <66 dB和THD> 72 dB。该ADC采用13-GHz，1- / splμ/ m BiCMOS工艺实现，尺寸为7mm / sup 2 /，同时从5.0 V单电源消耗300 mW的功率。

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来源
《IEEE Journal of Solid-State Circuits》 |1997年第12期|P.1876-1886|共11页
作者
Vorenkamp P.; Roovers R.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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1. A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture [J] . Nakajima Y., Sakaguchi A., Ohkido T., Solid-State Circuits, IEEE Journal of . 2010,第4期

机译：具有级联校准的折叠-插值架构的后台自校准6b 2.7 GS / s ADC
2. Ultra-wideband calibration-free 6-bit 4GSps folding-interpolating ADC [J] . Xiangmin Li, Zhuang Kang, Liang Jia Electronics world . 2019,第1989期

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3. Ultra-wideband calibration-free 6-bit 4GSps folding-interpolating ADC [J] . Xiangmin Li, Zhuang Kang, Liang Jia Electronics world . 2019,第1989期

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4. A self-background calibrated 6b 2.7GS/s ADC with cascade-calibrated folding-interpolating architecture [C] . Symposium on VLSI Circuits . 2009

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5. A single-channel 10b 1GS/s ADC with 2-cycle latency using pipelined cascaded folding architecture [D] . Razzaghi, Alireza 2008

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6. Design of Reconfigurable Time-to-Digital Converter Based on Cascaded Time Interpolators for Electrical Impedance Spectroscopy † [O] . Sounghun Shin, Yoontae Jung, Soon-Jae Kweon, 2020

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7. Circuit design of Track-And-Hold Amplifier in Ultra-High-speed Folding-Interpolating ADC [O] . Yongcong Liu, Jianye Wang, Hao Ding 2016

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A 12-b, 60-MSample/s cascaded folding and interpolating ADC

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