A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 /spl mu/m n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 /spl mu/W/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 /spl mu/W/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm/sup 2//pole for both designs.
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机译：提出了一种使用数字CMOS技术的低功耗连续时间滤波器的设计技术。基本构建模块是一个完全平衡的积分器，其单位增益频率由小信号跨导和MOSFET栅极电容确定。使用平衡的信号路径可减少积分器多余的相移，而使用低压共源共栅放大器则可增加开环增益。两极带通和五极低通梯形滤波器已在1.2 / spl mu / m n阱CMOS工艺中实现。低通原型提供300 kHz-1000 kHz偏置电流可调-3 dB带宽，67 dB动态范围和1％的总谐波失真（THD），以及30 / spl mu / W / pole（300 kHz带宽）的功耗， 1.5 V电源；带通原型的可调中心频率为300 kHz-1000 kHz，Q为8.5，1.5 V电源的功耗为75 / spl mu / W / pole（525 kHz中心频率）。两种设计的有源滤波器面积均为0.1 mm / sup 2 //极。
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