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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI
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A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

机译：一个基于GaAs LSI的B-ISDN的2.5 Gb / s ATM分插单元

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摘要

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 /spl mu/m E/D MESFET process.
机译：本文介绍了高速GaAs异步传输模式（ATM）多路复用多路ASIC（AMDA）的设计和实现，它是高速ATM分插单元（ADU）中的核心LSI电路。该单元用于宽带交换系统的新型分布式ATM多路复用-多路分解结构中。 ADU在以不同数据速率运行的系统之间提供基于单元的接口（高速接口为2.5 Gb / s，低速接口为155/622 Mb / s），或可用于构建本地高速网络。速度开关和局域网。自定时先进先出（FIFO）缓冲区用于处理以不同时钟速率运行的域之间的速度差距，并且在所有高速芯片上都使用接收器输入（STARI）接口自定时，芯片间链接，以消除时序偏差。已开发出具有分布式多路复用-多路分离架构中的两个ADU的印刷电路板（PCB），AMDA演示了在4 Gb / s（500 MHz时钟频率）以上的操作以及在标准0.8 /秒下具有5 W的相关功耗。 spl mu / m E / D MESFET工艺。

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