In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-/spl mu/m CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16/spl times/16)-b multiplier using the Booth algorithm, a (6/spl times/6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6/spl times/6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS.
展开▼
机译：在本文中，我们介绍了用于CMOS低功耗高性能乘法器设计的电路技术。使用0.8- / spl mu / m CMOS（在BiCMOS中）技术对新型全加法器电路进行了仿真和制造。与传统的CMOS全加法器相比，互补式传输晶体管逻辑传输门（CPL-TG）全加法器实现了50％的节能。与静态CMOS实施相比，布斯编码器的CPL实施可节省30％的功率，速度提高15％。尽管使用Booth算法为（16 / spl times / 16）-b乘法器对电路进行了优化，但为了减少仿真时间，使用（6 / spl times / 6）-b的实现方式作为测试工具。对于（6 / spl times / 6）-b的情况，基于CPL-TG的实现比传统CMOS节省了18％的功耗，并提高了30％的速度。
展开▼
