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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Low-jitter process-independent DLL and PLL based on self-biased techniques
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Low-jitter process-independent DLL and PLL based on self-biased techniques

机译：基于自偏置技术的低抖动，与过程无关的DLL和PLL

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摘要

Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL designs achieve process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and, most importantly, low input tracking jitter. Both the damping factor and the bandwidth to operating frequency ratio are determined completely by a ratio of capacitances. Self-biasing avoids the necessity for external biasing, which can require special bandgap bias circuits, by generating all of the internal bias voltages and currents from each other so that the bias levels are completely determined by the operating conditions. Fabricated in a 0.5-/spl mu/m N-well CMOS gate array process, the PLL achieves an operating frequency range of 0.0025 MHz to 550 MHz and input tracking jitter of 384 ps at 250 MHz with 500 mV of low frequency square wave supply noise.
机译：提出了基于自偏置技术的延迟锁定环（DLL）和锁相环（PLL）设计。 DLL和PLL设计实现了工艺技术独立性，固定的阻尼因数，固定的带宽与工作频率之比，较宽的频率范围，输入相位偏移消除以及最重要的是低输入跟踪抖动。阻尼因数和带宽与工作频率之比完全取决于电容的比值。自偏置通过相互产生所有内部偏置电压和电流，从而避免了外部偏置的需要，而外部偏置可能需要特殊的带隙偏置电路，因此偏置水平完全由工作条件决定。 PLL采用0.5- / splμm/ m的N阱CMOS门阵列工艺制造，可实现0.0025 MHz至550 MHz的工作频率范围，在250 MHz时具有500 mV的低频方波电源，输入跟踪抖动为384 ps。噪声。

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