A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET

Murata K.; Otsuji T.

首页> 外文期刊>IEEE Journal of Solid-State Circuits >A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET

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A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET

机译：一种新颖的高速锁存操作触发器（HLO-FF）电路及其在使用0.2- / spl mu / m GaAs MESFET的19 Gb / s判定电路中的应用

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This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s.

机译：本文描述了一种新颖的高速触发器电路，称为GaAs低功率源耦合FET逻辑（LSCFL）的高速锁存操作触发器（HLO-FF）。我们使用新提出的解析传播延迟时间表达式来揭示HLO-FF的高速运行机制。还提出了基于这些表达式的串联门控主从触发器和HLO-FF的设计方法。 SPICE仿真和两个决策IC的制造证实了我们分析方法的准确性以及HLO-FF决策电路在19 Gb / s时的高速运行。

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《IEEE Journal of Solid-State Circuits》 |1995年第10期|P.1101-1108|共8页
作者
Murata K.; Otsuji T.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
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4. A Novel High-Speed Latching Operation Flip-Flop (HLO-FF) Circuit and its Application to a 19 Gb/s Decision Circuit Using 0.2 /spl mu/ Gaas Mesfet [C] . Murata, K., Otsuji, . 2001

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5. Structural delay testing of latch-based high-speed circuits with time borrowing. [D] . Chung, Kun Young. 2008

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A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET

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