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首页> 外文期刊>Solid-State Electronics >Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance
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Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance

机译：具有非均匀栅极电容的隧道FET，可改善器件和电路级性能

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摘要

We report the significant improvement obtained by a non-uniform gate capacitance made by appropriate combination of high-k and low-k regions over the tunneling and the channel regions of a heterostucture TFET (called HKLKTFET). In addition to significantly enhanced I_(ON) and subthreshold swing, we find that this structure offers great improvements for the dynamic switching energy (66% saving) and propagation delay (~3× fast operation) compared to a heterostructure TFET (HeTFET) due to the reduction of the Miller effect. We compare and benchmark the proposed device against a 65 nm low stand-by power (LSTP) CMOS technology, and we show that at a supply voltage of V_(DD)= 0.4 V, TFETs can have smaller propagation delays compared to CMOS operating in the subthreshold region. Higher cut-off frequency (～3×) and bandwidth for analog applications is observed in circuit-level simulations.
机译：我们报告了通过异质结构TFET（称为HKLKTFET）的隧穿和沟道区域上的高k和低k区域的适当组合所产生的非均匀栅极电容所获得的显着改进。除了显着增强I_（ON）和亚阈值摆幅之外，我们发现与异质结构TFET（HeTFET）相比，这种结构还极大地改善了动态开关能量（节省66％）和传播延迟（〜3倍快速操作）降低米勒效应。我们将拟议的器件与65nm低待机功率（LSTP）CMOS技术进行了比较和基准测试，结果表明，在V_（DD）= 0.4 V的电源电压下，与在CMOS中工作的CMOS相比，TFET的传播延迟更短。亚阈值区域。在电路级仿真中，可以看到模拟应用具有更高的截止频率（〜3x）和带宽。

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  • 来源
    《Solid-State Electronics》 |2013年第6期|205-210|共6页
  • 作者

    C. Alper; L De Michielis; N. Dagtekin; L Lattanzio; D. Bouvet; A.M. Ionescu;

  • 作者单位

    Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne CH-1015, Switzerland;

    Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne CH-1015, Switzerland;

    Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne CH-1015, Switzerland;

    Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne CH-1015, Switzerland;

    Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne CH-1015, Switzerland;

    Nanoelectronic Devices Laboratory (Nanolab), Ecole Polytechnique Federale de Lausanne (EPFL), Lausanne CH-1015, Switzerland;

  • 收录信息 美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

    Tunnel Field-Effect Transistor (TFET); Oxide capacitance; High-k oxide; Finite element simulation;

    机译：隧道场效应晶体管（TFET）;氧化电容高钾氧化物有限元模拟;

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