Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi_2 tunnel junctions

L Knoll; M. Schmidt; Q.T. Zhao; S. Trellenkamp; A. Schaefer; K.K. Bourdelle; S. Mantr

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Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi_2 tunnel junctions

机译：使用隔离掺杂的NiSi_2隧道结，具有高导通电流和50 mV / dec斜率的Si隧道晶体管

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Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped nickel disilicide (NiSi_2) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly simplifies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: dopant segregation based on the "snow-plough" effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffu-sion. High drive currents of up to 60 μA/um of planar p-TFETs were achieved indicating good silicide/sil-icon tunneling junctions. The non-linear temperature dependence of the inverse subthreshold slope S indicates characteristic TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO_2/TiN gates show high drive currents of 7 μA/μm @ 1 V V_(dd) and steep inverse subthreshold slopes with minimum values of <50 mV/dec due to the smaller band gap of strained Si and optimized electrostatics.

机译：平面和纳米线（NW）隧穿场效应晶体管（TFET）已在具有薄掺杂二硅化镍（NiSi_2）源极和漏极（S / D）触点的超薄应变和非应变SOI上制造。我们开发了一种新颖的自对准工艺来形成p-i-n TFET，通过使用高k /金属栅作为荫罩和掺杂剂隔离的倾斜掺杂剂注入大大简化了它们的制造。比较了两种掺杂剂偏析方法：基于硅化物在硅化过程中的“雪effect”效应和注入到硅化物（IIS）中，然后进行热扩散的掺杂剂偏析。实现了高达60μA/ um的平面p-TFET的高驱动电流，表明良好的硅化物/硅图标隧穿结。反亚阈值斜率S的非线性温度依赖性表示特征TFET行为。具有Ω型HfO_2 / TiN栅极的应变Si NW阵列n-TFET在1 V V_（dd）时显示出7μA/μm的高驱动电流，并且由于带隙较小，反向亚阈值斜率极小，最小值<50 mV / dec应变硅和优化的静电。

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来源
《Solid-State Electronics》 |2013年第6期|211-215|共5页
作者
L Knoll; M. Schmidt; Q.T. Zhao; S. Trellenkamp; A. Schaefer; K.K. Bourdelle; S. Mantr;
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作者单位

Peter Gruenberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Juelich, 52425Juelich, Germany;

Peter Gruenberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Juelich, 52425Juelich, Germany;

Peter Gruenberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Juelich, 52425Juelich, Germany;

Peter Gruenberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Juelich, 52425Juelich, Germany;

Peter Gruenberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Juelich, 52425Juelich, Germany;

SOITEC, Pare Technologique des Fontaines, 38190 Bernin, France;

Peter Gruenberg Institut 9 (PGI-9/IT), JARA-FIT, Forschungszentrum Juelich, 52425Juelich, Germany;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);美国《生物学医学文摘》(MEDLINE);
原文格式 PDF
正文语种 eng
中图分类
关键词
Dopant-segregation; Tilted implantation; Nanowire TFET; Nickel silicide;

机译：掺杂物分离;倾斜植入纳米线TFET;硅化镍;

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1. A Non-Hysteretic Sub-60-mV/decade Subthreshold Slope and ON-Current Boosts in Electrostrictive-Piezoelectric Transistors [J] . Raj K. Jana Electron Device Letters, IEEE . 2017,第12期

机译：电致伸缩压电晶体管的非迟滞低于60mV /十年的亚阈值斜率和导通电流提升
2. Broken-Gap Tunnel MOSFET: A Constant-Slope Sub-60-mV/decade Transistor [J] . Smith J. T., Das S., Appenzeller J. Electron Device Letters, IEEE . 2011,第10期

机译：裂隙隧道MOSFET：恒定斜率低于60mV /十倍频程的晶体管
3. Tunneling Field-Effect Transistors With an of 50 and a Subthreshold Swing of 86 mV/dec Using Gate Oxide [J] . Zhao H., Chen Y., Wang Y., Electron Device Letters, IEEE . 2010,第12期

机译：使用栅极氧化物隧穿50的场效应晶体管和86mV / dec的亚阈值摆幅的隧道效应晶体管
4. Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped Nisi2 tunnel junctions [C] . Knoll L., Zhao Q. T., Trellenkamp S., 2012 Proceedings of the European Solid-State Device Research Conference. . 2012

机译：使用隔离掺杂的Nisi2隧道结，具有高导通电流和50 mV / dec的斜率的Si隧道晶体管
5. Atomic scale understanding of nanostructures in a double barrier tunneling junction: Scanning tunneling microscopy of alkali doped buckminsterfullerenes on partially oxidized nickel aluminide(110). [D] . Liu, Ning. 2005

机译：双势垒隧穿结中纳米结构的原子尺度理解：部分氧化的铝化镍上碱掺杂的buckminsterfullerenes的扫描隧穿显微镜（110）。
6. A Steep-Slope Transistor Combining Phase-Change and Band-to-Band-Tunneling to Achieve a sub-Unity Body Factor [O] . Wolfgang A. Vitale, Emanuele A. Casu, Arnab Biswas, -1

机译：结合了相变和带间隧道效应的陡坡晶体管以实现亚单位体积因数
7. 1D Broken-gap Tunnel Transistor with MOSFET-like On-currents and Sub-60mV/dec Subthreshold Swing [O] . Siyuranga O. Koswatta, Steven J. Koester, Wilfried Haensch 2015

机译：1D断裂隧道晶体管，具有类似mOsFET的导通电流和低于60mV / dec的亚阈值摆幅

Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi_2 tunnel junctions

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