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首页> 外文期刊>Solid-State Electronics >High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs
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High gate voltage drain current leveling off and its low-frequency noise in 65 nm fully-depleted strained and non-strained SOI nMOSFETs

机译：在65 nm全耗尽应变和非应变SOI nMOSFET中，高栅极电压漏极电流趋于平稳，并且其低频噪声

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摘要

For fully-depleted SOI MOSFETs, fabricated in standard and strained 65 nm technologies, it is observed that the drain current I normalized for the device length L and width W levels off at sufficiently high gate voltage overdrives. Also the normalized drain current 1/f noise spectral density S_I shows a plateau value for high front gate voltages. For both strained and non-strained devices there exists a relation between the two plateau values and a ,y～(x)~(1/4) law is found for the experimental data where x = S_I~(plateau)(L~3/WN_(ot)), y = I~(plateau) (L/W ), S_I~(plateau) and I~(plateau) are the plateau values of S_I and I, respectively, and N_(ot) is the density of the oxide traps responsible for the 1/f noise observed. Compared to standard SOI the use of strained SOI (sSOI) increases the magnitude of the plateau and makes its dependence on the device geometry more pronounced, while the impact of a strained contact etch stop layer (sCESL) is limited. The experimental observations are explained by taking into consideration the field and geometry dependence of the mobility and the influence of negative oxide charges on the drain current.
机译：对于采用标准和应变65 nm技术制造的全耗尽SOI MOSFET，可以观察到，在足够高的栅极电压过驱动下，针对器件长度L和宽度W标准化的漏极电流I趋于稳定。归一化的漏极电流1 / f噪声频谱密度S_I也显示出高前栅极电压的平稳值。对于应变和非应变装置，两个平台值之间存在关系，并且对于x = S_I〜（plateau）（L〜3）的实验数据，发现y〜（x）〜（1/4）定律/ WN_（ot）），y = I〜（高原）（L / W），S_I〜（高原）和I〜（高原）分别是S_I和I的高原值，N_（ot）是密度导致所观察到的1 / f噪声的氧化物陷阱的数量。与标准SOI相比，应变SOI（sSOI）的使用增加了平台的幅度，并使其对器件几何形状的依赖性更加明显，而应变接触蚀刻停止层（sCESL）的影响却受到了限制。通过考虑迁移率的场强和几何形状依赖性以及负氧化物电荷对漏极电流的影响来解释实验观察。

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