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首页> 外文期刊>Superlattices and microstructures >Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation
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Interface trap charge-based reliability assessment of high-k dielectric-modulated nanoscaled FD SOI MOSFET for low power digital ICs: Modeling and simulation

机译：基于陷阱电荷的高功率数字ICS的高k电介质调制纳米级FD SOI MOSFET的临界陷阱电荷的可靠性评估：建模与仿真

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摘要

This paper proposes the analytical surface potential and threshold-voltage model for performance investigation of gate stack (GS) dual-metal-insulated-gate (DMIG) source-engineered (SE) Fully-depleted silicon-on-insulator (FD SOI) MOSFET for low-power digital applications. In which, a new concept of dielectric-modulated high-k insulator-gap with source engineering has been analytically formulated for the first time in dual-metal-gate technology-based FD SOI MOSFET. The surface potential model is developed using two-dimensional Poisson's equations with including effects of interface trap charges (ITCs) and verified against numerical simulations over the TCAD tool from Silvaco ATLAS™. Also, the parametric analysis has been performed to optimize the device dimensions for better nanoscaled MOS design. Further, a six transistor (6-T) SRAM cell is designed using n/p-GS-DMIG~(SE) FD SOI MOSFET for the analysis of static-noise-margin (SNM). It is observed that the proposed FD SOI MOSFET offers excellent immunity towards short-channel-effects (SCEs) along with improved SRAM circuit performance at different ITC conditions.
机译：本文提出了用于栅极堆叠（GS）双金属绝缘栅极（DMIG）源工程（SE）全耗尽的绝缘体（FD SOI）MOSFET的分析表面电位和阈值 - 电压模型用于低功耗数字应用。其中，在基于双金属栅极技术的FD SOI MOSFET中首次进行了分析地配制了具有源工程的介质调制的高k绝缘体间隙的新概念。表面电位模型采用二维泊松等式开发，包括接口陷阱电荷（ITC）的效果，并通过来自Silvaco Atlas™的TCAD工具验证了与数值模拟。而且，已经进行了参数分析以优化用于更好的纳米级MOS设计的装置尺寸。此外，使用N / P-GS-DMIG〜（SE）FD SOI MOSFET设计了六个晶体管（6-T）SRAM单元，用于分析静电噪声裕度（SNM）。据观察，所提出的FD SOI MOSFET在不同ITC条件下提高了SRAM电路性能的短信效应（SCES）提供了极好的抗扰度。

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  • 来源
    《Superlattices and microstructures》 |2021年第6期|106871.1-106871.15|共15页
  • 作者

    Nilesh Anand Srivastava; Anjali Priya; Ram Awadh Mishra;

  • 作者单位

    PARAM Lab Electronics and Communication Engineering Department Motilal Nehru National Institute of Technology Allahabad 211004 India;

    CASEST School of Physics University of Hyderabad Hyderabad 500046 India;

    PARAM Lab Electronics and Communication Engineering Department Motilal Nehru National Institute of Technology Allahabad 211004 India;

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  • 原文格式 PDF
  • 正文语种 eng
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  • 关键词

    DMIG; FD SOI; Gate-stack; SCEs; SRAM;

    机译：DMIG;FD SOI;门堆;sces;SRAM.;

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