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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Sequential Element Design With Built-In Soft Error Resilience
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Sequential Element Design With Built-In Soft Error Resilience

机译：具有内置软错误恢复能力的顺序元素设计

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摘要

This paper presents a built-in soft error resilience (BISER) technique for correcting radiation-induced soft errors in latches and flip-flops. The presented error-correcting latch and flip-flop designs are power efficient, introduce minimal speed penalty, and employ reuse of on-chip scan design-for-testability and design-for-debug resources to minimize area overheads. Circuit simulations using a sub-90-nm technology show that the presented designs achieve more than a 20-fold reduction in cell-level soft error rate (SER). Fault injection experiments conducted on a microprocessor model further demonstrate that chip-level SER improvement is tunable by selective placement of the presented error-correcting designs. When coupled with error correction code to protect in-pipeline memories, the BISER flip-flop design improves chip-level SER by 10 times over an unprotected pipeline with the flip-flops contributing an extra 7-10.5% in power. When only soft errors in flips-flops are considered, the BISER technique improves chip-level SER by 10 times with an increased power of 10.3%. The error correction mechanism is configurable (i.e., can be turned on or off) which enables the use of the presented techniques for designs that can target multiple applications with a wide range of reliability requirements
机译：本文提出了一种内置的软错误恢复能力（BISER）技术，用于校正锁存器和触发器中辐射引起的软错误。提出的纠错锁存器和触发器设计具有高能效，引入了最小的速度损失，并利用了片上扫描的可测试性和调试资源的重用，以最大程度地减少了面积开销。使用90纳米以下技术的电路仿真表明，提出的设计将单元级软错误率（SER）降低了20倍以上。在微处理器模型上进行的故障注入实验进一步证明，通过选择性放置所提出的纠错设计，可以调节芯片级SER。 BISER触发器与纠错码一起保护流水线内存储器时，其芯片级SER比未受保护的流水线提高了10倍，并且触发器还提供了额外的7-10.5％的功耗。当仅考虑触发器中的软错误时，BISER技术可将芯片级SER提升10倍，功率增加10.3％。纠错机制是可配置的（即可以打开或关闭），从而可以将提出的技术用于设计，这些设计可以针对具有广泛可靠性要求的多种应用

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