Sleep switch dual threshold Voltage domino logic with reduced standby leakage current

著录项

• 来源
  《IEEE transactions on very large scale integration (VLSI) systems》 |2004年第5期|p.485-496|共12页
• 作者

  Kursun V.; Friedman E.G.;

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• 作者单位

  Dept. of Electr. & Comput. Eng., Univ. of Rochester, NY, USA;

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• 收录信息
• 原文格式 PDF
• 正文语种 eng
• 中图分类 微电子学、集成电路（IC）;
• 关键词

  power consumption; leakage currents; CMOS integrated circuits; integrated circuit noise; integrated logic circuits; transistor circuits; VLSI; sleep switch dual threshold voltage; leakage current; subthreshold leakage energy consumption; domino logic circuits; sleep switch transistors; dual threshold voltage domino logic circuit; threshold voltage CMOS technology; sleep switch circuit; power consumption; leakage sleep mode; subthreshold leakage energy;

  机译：功耗;漏电流;CMOS集成电路;集成电路噪声;集成逻辑电路;晶体管电路;VLSI;睡眠开关双阈值电压;漏电流;亚阈值泄漏能耗;多米诺逻辑电路;睡眠开关晶体管;双阈值电压多米诺逻辑电路;阈值电压CMOS技术;睡眠开关电路;功耗;漏电睡眠模式;亚阈值泄漏能量;