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Systematic IEEE rounding method for high-speed floating-point multipliers

机译：高速浮点乘法器的系统IEEE四舍五入方法

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For performance reasons, many high-speed floating-point multipliers today precompute multiple significand values (SVs) in advance. The final normalization and rounding steps are then performed by selecting the appropriate SV. While having speed advantages, this integrated rounding method complicates the development of the rounding logic significantly, hence, requiring a systematic rounding method. The systematic rounding method, presented in this paper, has three steps: 1) constructing a rounding table; 2) developing a prediction scheme; and 3) performing rounding digits selection (RDS). The rounding table lists all possible SVs that need to be precomputed. Prediction reduces the number of these SVs for efficient hardware implementation while RDS reduces the complexity of the rounding logic. Both prediction and RDS depend on the specifics of the hardware implementation. Two hardware implementations are described. The first one is modeled after that reported by Santoro et al. and the second improved one supports all IEEE rounding modes. Besides allowing systematic hardware optimization, this rounding method has the added advantage that verification and generalization are straightforward.
机译：出于性能原因，当今许多高速浮点乘法器预先预先计算了多个有效值（SV）。然后，通过选择适当的SV来执行最终的归一化和舍入步骤。尽管具有速度优势，但是这种集成的舍入方法使舍入逻辑的开发变得非常复杂，因此，需要系统的舍入方法。本文提出的系统化舍入方法包括三个步骤：1）建立一个舍入表； 2）制定预测方案； 3）执行四舍五入数字选择（RDS）。舍入表列出了需要预先计算的所有可能的SV。预测减少了这些SV的数量，以实现有效的硬件实现，而RDS减少了舍入逻辑的复杂性。预测和RDS都取决于硬件实现的细节。描述了两种硬件实现。第一个模型是根据Santoro等人的报道建模的。第二个改进的版本支持所有IEEE舍入模式。除了允许系统的硬件优化之外，这种舍入方法还具有验证和泛化简单明了的优点。

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