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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Multiple-symbol parallel decoding for variable length codes
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Multiple-symbol parallel decoding for variable length codes

机译：可变长度码的多符号并行解码

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摘要

In this paper, a multiple-symbol parallel variable length decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit block of encoded input data stream. The proposed method partially breaks the recursive dependency related to the VLD. First, all possible codewords in the block are detected in parallel and lengths are returned. The procedure results redundant number of codeword lengths from which incorrect values are removed by recursive selection. Next, the index for each symbol corresponding the detected codeword is generated from the length determining the page and the partial codeword defining the offset in symbol table. The symbol lookup can be performed independently from symbol table. Finally, the sum of the valid codeword lengths is provided to an external shifter aligning the encoded input stream for a new decoding cycle. In order to prove feasibility and determine the limiting factors of our proposal, the variable length decoder has been implemented on an field-programmable gate-array (FPGA) technology. When applied to MPEG-2 standard benchmark scenes, on average 4.8 codewords are decoded per cycle resulting in the throughput of 106 million symbols per second.
机译：本文介绍了一种多符号并行可变长度解码（VLD）方案。该方案能够解码N位编码输入数据流块中的所有码字。所提出的方法部分地打破了与VLD相关的递归依赖性。首先，并行检测块中所有可能的码字，并返回长度。该过程会产生大量的代码字长度，通过递归选择从中删除不正确的值。接下来，根据确定页的长度和定义符号表中的偏移量的部分代码字，生成与检测到的代码字相对应的每个符号的索引。可以独立于符号表执行符号查找。最后，将有效码字长度的总和提供给外部移位器，以将编码的输入流对齐一个新的解码周期。为了证明可行性并确定我们建议的限制因素，可变长度解码器已在现场可编程门阵列（FPGA）技术上实现。当应用于MPEG-2标准基准场景时，每个周期平均解码4.8个码字，从而每秒产生1.06亿个符号的吞吐量。

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