Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead

Ozev S.; Orailoglu A.

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Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead

机译：具有受限硬件开销的线性模拟电路并行测试硬件的设计

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Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for automatic design of concurrent failure detection circuitry for linear analog systems is discussed in this paper. The desired hardware bound is specified as a constraint; the methodology aims at providing coverage in terms of all the circuit components while minimizing the loading overhead by reducing the number of internal circuit nodes that need to be tapped. Parameter tolerances are incorporated through either statistical or mathematical analysis to determine the threshold for failure alarm.

机译：随着对安全至关重要的系统的普及，并行检测模拟电路中的故障变得越来越重要。本文讨论了一种用于线性模拟系统并发故障检测电路自动设计的方法。所需的硬件绑定被指定为约束；该方法旨在提供所有电路组件的覆盖范围，同时通过减少需要分接的内部电路节点的数量来最大程度地减少负载开销。通过统计或数学分析来合并参数公差，以确定故障警报的阈值。

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《IEEE transactions on very large scale integration (VLSI) systems》 |2004年第7期|p.756-765|共10页
作者
Ozev S.; Orailoglu A.;
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正文语种 eng
中图分类微电子学、集成电路（IC）;
关键词
analogue integrated circuits; failure analysis; integrated circuit design; integrated circuit testing; concurrent failure detection circuitry; concurrent test hardware; constraint hardware; failure alarm threshold; internal circuit node; linear analog circuit; mat;

机译：模拟集成电路;故障分析;集成电路设计;集成电路测试;并发故障检测电路;并发测试硬件;约束硬件;故障报警阈值;内部电路节点;线性模拟电路;垫子;

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8. State-of-the-Art Assessment of Testing and Testability of Custom LSI/VLSI Circuits. Volume II. Hardware Design Verification. [R] . Carlan, A. J. 1982

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Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead

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