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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Designing an asynchronous microcontroller using Pipefitter
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Designing an asynchronous microcontroller using Pipefitter

机译：使用Pipefitter设计异步微控制器

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摘要

This paper discusses how Pipefitter, a tool chain that implements a fully automated synthesis flow for asynchronous circuits, can be used to design a simple asynchronous microcontroller. The use of register transfer level (RTL)-like Verilog hardware description languages (HDL) as the input format makes the first steps of the design flow (i.e., specification and simulation) very easy for the designer. Pipefitter directly synthesizes the control unit as a hazard-free standard cell netlist, uses a genetic algorithm to perform binding and multiplexer optimization for the datapath and allows the user to manually specify the binding. It also produces a synthesizable Verilog specification for the datapath, as well as a set of scripts driving both its synthesis and timing analysis by state-of-the-art commercial synchronous RTL and logic synthesis tools. The automated insertion of matched delays completes the logic design, and hands off the netlist to the standard cell-based layout tools. The example presented in this brief, shows how Pipefitter can be effectively used for the design of asynchronous application specific integrated circuits.
机译：本文讨论了如何将Pipefitter（一种为异步电路实现全自动综合流程的工具链）用于设计简单的异步微控制器。使用类似于寄存器传输级别（RTL）的Verilog硬件描述语言（HDL）作为输入格式，对于设计人员来说，设计流程的第一步（即规范和仿真）非常容易。 Pipefitter直接将控制单元合成为无危害的标准单元网表，使用遗传算法对数据路径执行绑定和多路复用器优化，并允许用户手动指定绑定。它还为数据路径生成了可综合的Verilog规范，以及通过最新的商业同步RTL和逻辑综合工具来驱动其综合和时序分析的脚本集。匹配延迟的自动插入可完成逻辑设计，并将网表移交给标准的基于单元的布局工具。本摘要中提供的示例说明了如何将Pipefitter有效地用于异步专用集成电路的设计。

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