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Power estimation techniques for FPGAs

机译：FPGA的功耗估算技术

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摘要

The dynamic power consumed by a digital CMOS circuit is directly proportional to both switching activity and interconnect capacitance. In this paper, we consider early prediction of net activity and interconnect capacitance in field-programmable gate array (FPGA) designs. We develop empirical prediction models for these parameters, suitable for use in power-aware layout synthesis, early power estimation/planning, and other applications. We examine how switching activity on a net changes when delays are zero (zero delay activity) versus when logic delays are considered (logic delay activity) versus when both logic and routing delays are considered (routed delay activity). We then describe a novel approach for prelayout activity prediction that estimates a net's routed delay activity using only zero or logic delay activity values, along with structural and functional circuit properties. For capacitance prediction, we show that prediction accuracy is improved by considering aspects of the FPGA interconnect architecture in addition to generic parameters, such as net fanout and bounding box perimeter length. We also demonstrate that there is an inherent variability (noise) in the switching activity and capacitance of nets that limits the accuracy attainable in prediction. Experimental results show the proposed prediction models work well given the noise limitations.
机译：数字CMOS电路消耗的动态功率与开关活动和互连电容都成正比。在本文中，我们考虑了现场可编程门阵列（FPGA）设计中网络活动和互连电容的早期预测。我们针对这些参数开发了经验预测模型，适用于功耗感知布局综合，早期功耗估算/计划以及其他应用。我们研究了当延迟为零（零延迟活动），考虑逻辑延迟（逻辑延迟活动）以及同时考虑逻辑和路由延迟（路由延迟活动）时，网络上的交换活动如何变化。然后，我们描述一种用于布局前活动预测的新颖方法，该方法仅使用零或逻辑延迟活动值以及结构和功能电路属性来估计网络的路由延迟活动。对于电容预测，我们表明，除了通用参数（如净扇出和边界框周长）外，还考虑了FPGA互连体系结构的各个方面，从而提高了预测精度。我们还证明，开关活动和网络电容存在固有的可变性（噪声），这会限制预测中可获得的准确性。实验结果表明，在噪声限制的情况下，所提出的预测模型效果良好。

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