...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >Error Probability Models for Voltage-Scaled Multiply-Accumulate Units
【24h】

Error Probability Models for Voltage-Scaled Multiply-Accumulate Units

机译：电压缩放乘积单元的误差概率模型

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Energy efficiency is a critical design objective in deep learning hardware, particularly for real-time machine learning applications where the processing takes place on resource-constrained platforms. The inherent resilience of these applications to error makes voltage scaling an attractive method to enhance efficiency. Timing error probability models are proposed in this article to better understand the effects of voltage scaling on error rates and power consumption of multiply-accumulate units. The accuracy of the proposed models is demonstrated via Monte Carlo simulations. These models are then used to quantify the related tradeoffs without relying on time-consuming hardware-level simulations. Both modern FinFET and emerging tunneling field-effect transistor (TFET) technologies are considered to explore the dependence of the effects of voltage scaling on these two technologies.
机译：能效是深度学习硬件中的关键设计目标，特别是对于在资源受限平台上进行处理的实时机器学习应用。这些应用于误差的固有恢复使电压缩放提高效率的有吸引力的方法。本文提出了定时误差概率模型，以更好地了解电压缩放对频率累积单元的误差速率和功耗的影响。通过Monte Carlo模拟证明了所提出的模型的准确性。然后使用这些模型来量化相关权衡而不依赖于耗时的硬件级模拟。现代FinFET和新兴隧道场效应晶体管（TFET）技术被认为是探讨电压缩放对这两种技术影响的依赖性。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号