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首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems
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An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems

机译：具有用于许多核心系统的低功率混合无线有线时钟分配网络的活性硅插入器

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摘要

Due to the increasing interconnect delay caused by shrinking wiring dimensions, modern synchronous many-core systems are now facing critical issues. Particularly, the power budget to propagate high-frequency clock signals across the chip is limited. It becomes more challenging using conventional metallic interconnects to deliver a clock with low uncertainties across active dies. This article proposes a novel hybrid wireless-wired clock distribution network, which improves the performance of ON-chip clock distribution significantly. By using embedded wireless clock transmitter and receiver designs, because of the high fan-out feature of the wireless clock transmission, the overall clock delay, skew, and power have been reduced. The proposed hybrid clock distribution scheme is verified through a novel test circuit by using Arm Mali-G77 GPU as an example. Experimental results indicate that the proposed clock distribution network exhibits a significant global delay reduction of up to 28.8%. Also, for the best case scenario, a maximum of 46.7% and 17.7% reduction in clock skew and power consumption, are identified, respectively. Thus, our proposed approach offers a promising solution to clock distribution for many-core integrated circuits, especially for high-performance systems.
机译：由于接线尺寸收缩延迟的互连延迟增加，现代同步许多核心系统现在面临着关键问题。特别是，在芯片上传播高频时钟信号的功率预算是有限的。使用传统的金属互连变得更具挑战性，以在有源模具中输送具有低不确定性的时钟。本文提出了一种新型混合无线有线时钟分配网络，可显着提高片上时钟分布的性能。通过使用嵌入式无线时钟发射器和接收器设计，由于无线时钟传输的高扇出特征，总时钟延迟，偏斜和功率已经降低。通过使用ARM MALI-G77 GPU作为示例，通过新型测试电路通过新型测试电路来验证所提出的混合时钟分布方案。实验结果表明，所提出的时钟配送网络表现出显着的全球延迟减少，高达28.8％。此外，对于最佳案例场景，分别确定时钟偏斜和功耗降低的46.7％和17.7％。因此，我们所提出的方法提供了对多核集成电路的时钟分布的有希望的解决方案，特别是对于高性能系统。

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