Hardware implementation of various neural network with on-chip learning

ALIN TISAN; STEFAN ONIGA; CIPRIAN GAVRINCEA

首页> 外文期刊>WSEAS Transactions on Signal Processing >Hardware implementation of various neural network with on-chip learning

【24h】

Hardware implementation of various neural network with on-chip learning

机译：具有片上学习功能的各种神经网络的硬件实现

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

In this paper we propose a method to implement different neural network in FPGA circuits: a feedforward neural network with on-chip delta and Hebbian rule learning algorithm. The method implies the building of a neural network by generic blocks designed in Mathworks' Simulink environment. The main characteristics of this solution are on-chip learning algorithm implementation and high reconfiguration capability and operation under real time constraints.

机译：在本文中，我们提出了一种在FPGA电路中实现不同神经网络的方法：具有片上增量和Hebbian规则学习算法的前馈神经网络。该方法意味着通过在Mathworks的Simulink环境中设计的通用模块构建神经网络。该解决方案的主要特征是片上学习算法的实现以及在实时约束下的高重配置能力和操作能力。

著录项

来源
《WSEAS Transactions on Signal Processing》 |2006年第10期|共7页
作者
ALIN TISAN; STEFAN ONIGA; CIPRIAN GAVRINCEA;
展开▼
作者单位

展开▼
收录信息
原文格式 PDF
正文语种 eng
中图分类声学;
关键词
MLP; Learning on-chip; Delta rule; Hebbian rule; ANN; FPGA;

机译：MLP;片上学习;Delta规则;Hebbian规则;ANN;FPGA;

相似文献

外文文献
中文文献
专利

1. Hardware implementation of new bell-shaped pulse mode neural network with on-chip learning and application to image processing [J] . Amir Gargouri, Mohamed Krid, Dorra Sellami Masmoudi International Journal of High Performance Systems Architecture . 2013,第3期

机译：具有片上学习功能的新型钟形脉冲模式神经网络的硬件实现及其在图像处理中的应用
2. An Efficient Three-Valued Multilayer Neural Network with On-Chip Learning Suitable for Hardware Implementation [J] . Hiroomi Hikawa Systems and Computers in Japan . 2000,第4期

机译：具有适合硬件实现的片上学习功能的高效三值多层神经网络
3. Comparing domain wall synapse with other non volatile memory devices for on-chip learning in analog hardware neural network [J] . Divya Kaushik, Utkarsh Singh, Upasana Sahu, AIP Advances . 2020,第2期

机译：与其他非易失性存储器件进行比较模拟硬件神经网络中的片上学习的域墙突触
4. Hardware implementation of an on-chip BP learning neural network with programmable neuron characteristics and learning rate adaptation [C] . Chun Lu, Bingxue Shi, Lu Chen . 2001

机译：具有可编程神经元特性和学习速率自适应的片上BP学习神经网络的硬件实现
5. Emerging Opportunities in Machine Learning Hardware Acceleration: From Advanced Neural Networks Implementation to Ultra-efficient Deep Learning Framework Using Next Generation Technology [D] . ?Cai, Ruizhe 2020

机译：机器学习硬件加速的新兴机会：从先进的神经网络实现，使用下一代技术实现超高效的深度学习框架
6. Probabilistic Spike Propagation for Efficient Hardware Implementation of Spiking Neural Networks [O] . Abinand Nallathambi, Sanchari Sen, Anand Raghunathan, 2021

机译：尖峰神经网络有效硬件实现的概率尖峰传播
7. Ferrimagnetic Synapse Devices for Fast and Energy-Efficient On-Chip Learning on An Analog-Hardware Neural Network [O] . Upasana Sahu, Naven Sisodia, Janak Sharda, 2021

机译：用于模拟硬件神经网络的Ferrimagnetic突触装置，用于快速和节能的片上学习
8. Analog hardware for learning neural networks [R] . 1991

机译：用于学习神经网络的模拟硬件

Hardware implementation of various neural network with on-chip learning

摘要

著录项

相似文献

相关主题

期刊订阅