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首页> 外文期刊>Journal of Low Power Electronics >Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses
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Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses

机译：基于时间冗余的片上总线峰值功率和延迟减少编码技术

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Power consumption and delay are two of the most important constraints in current-day on-chip bus design. The two major sources of dynamic power dissipation on a bus are the self capacitance and the coupling capacitance. As technology scales, the interconnect resistance increases due to shrinking wire-width. At the same time, spacing between the interconnects decreases resulting in an increase in the coupling capacitance. This, in turn, leads to stronger crosstalk effects between the interconnects. In Deep Sub-Micron technology the coupling capacitance exceeds the self capacitance, which, in turn, cause more power consumption and delay on the bus. Recently, the interest has also shifted to minimizing peak power dissipation. The reason being that higher peak power leads to an undesired increase in switching noise, metal electromigration problems and operation-induced variations due to non-uniform temperature on the die. Thus, minimizing power consumption and delay are the most important design objectives for on-chip buses. Several bus encoding schemes have been proposed in the literature for reducing crosstalk. Most of these encoding techniques use spatial redundancy that requires additional transmission wires on the bus. In this paper, a new temporal encoding scheme is proposed, which uses self-shielding memory-less codes to completely eliminate worst-case crosstalk effects and hence significantly minimizes power consumption and delay of the bus. A major advantage of the proposed temporal redundancy based encoding scheme is the reduction in the number of wires of the on-chip bus. This reduction facilitates extra spacing between the bus wires, when compared with the normal bus, for a given area. This, in turn, leads to reduced crosstalk effects between the wires. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks. The experimental results, when compared to the transmission over a normal bus, show that on an average the proposed technique leads to a reduction in the peak-power consumption by 51% (28%), 51% (29%), and 52% (30%) in the data (address) bus for 90 nm, 65 nm, and 45 nm technologies, respectively. For a bus length of 10 mm the proposed technique also achieves 17%, 31%, and 37% reduction in the bus delay for 90 nm, 65 nm, and 45 nm technologies, respectively, when compared to what is incurred by the data transmission on a normal bus.
机译：功耗和延迟是当今片上总线设计中最重要的两个约束。总线上动态功耗的两个主要来源是自电容和耦合电容。随着技术的发展，互连电阻会随着线宽的缩小而增加。同时，互连之间的间隔减小，从而导致耦合电容的增加。反过来，这导致互连之间的串扰效应更强。在深亚微米技术中，耦合电容超过了自电容，这反过来又导致更多的功耗和总线延迟。最近，人们的兴趣也转移到了最小化峰值功耗上。原因是较高的峰值功率会导致不必要的开关噪声，金属电迁移问题以及由于芯片温度不均匀而导致的操作引起的变化，这是不希望有的。因此，最小化功耗和延迟是片上总线最重要的设计目标。在文献中已经提出了几种用于减少串扰的总线编码方案。这些编码技术中的大多数使用空间冗余，这需要总线上的其他传输线。在本文中，提出了一种新的时间编码方案，该方案使用自屏蔽的无存储器代码来完全消除最坏情况的串扰效应，从而显着降低了功耗和总线延迟。所提出的基于时间冗余的编码方案的主要优点是减少了片上总线的导线数量。与普通母线相比，对于给定面积，这种减小有助于母线之间的额外间距。反过来，这导致导线之间的串扰效应减小。建议的编码方案已通过SPEC2000 CINT基准进行了测试。与通过普通总线进行传输相比，实验结果表明，所建议的技术平均可将峰值功耗降低51％（28％），51％（29％）和52％数据（地址）总线中（30％）分别用于90 nm，65 nm和45 nm技术。对于10 mm的总线长度，与数据传输相比，对于90 nm，65 nm和45 nm技术，所提出的技术还分别将总线延迟降低了17％，31％和37％。在普通巴士上。

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