...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices >Timing error analysis in digital-to-analog converter - effects of sampling clock jitter and timing skew (Glitch)
【24h】

Timing error analysis in digital-to-analog converter - effects of sampling clock jitter and timing skew (Glitch)

机译：数字到模拟转换器的定时误差分析 - 采样时钟抖动和定时偏移（毛刺）的效果

获取原文
获取原文并翻译 | 示例
   

获取外文期刊封面封底 >>

       
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

This paper describes two timing nonideality issues of Digital-to-Analog Converters (DACs); sampling clock jitter and clock skew effects. (i) A formula for the output error power due to sampling clock jitter is derived, and this has been validated by numerical simulation; spectrum characteristics of jitter-related noise are also examined. We have also found that when an analog low-pass filter follows the DAC and only the noise power inside the signal band is considered, increasing jitter and increasing input signal frequency degrade the DAC SNR. (ii) The clock timing skew inside the DAC causes glitch impulses. We try to characterize them by simulation and we have found the followings; as the input frequency increases, the effects of the glitch on the DAC SNR decrease. The effects of the glitch due to upper bits on the DAC SNR and SFDR are more significant than due to lower bits. Also glitch power is mainly located at the odd-multiple frequencies of the input signal.
机译：本文介绍了数模转换器（DAC）的两个时序非侵略性问题; 采样时钟抖动和时钟偏差效果。 （i）推导出由于采样时钟抖动引起的输出误差功率的公式，并且通过数值模拟验证了这一点; 还检查了抖动相关噪声的光谱特性。 我们还发现，当模拟低通滤波器遵循DAC并且仅考虑信号带内的噪声功率时，增加抖动和增加的输入信号频率降低DAC SNR。 （ii）DAC内的时钟定时偏斜导致毛刺冲动。 我们尝试通过模拟来对它们进行描述，我们找到了以下内容; 随着输入频率的增加，毛刺对DAC SNR的影响降低。 由于DAC SNR和SFDR上的上部位引起的毛刺的影响比较低的比特更重要。 毛刺电源主要位于输入信号的奇数频率。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号