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首页> 外文期刊>Journal of Low Power Electronics >Field Programmable Gate Array Softcore Processors Optimised for Digital Signal Processing Applications
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Field Programmable Gate Array Softcore Processors Optimised for Digital Signal Processing Applications

机译：现场可编程门阵列SoftCore处理器针对数字信号处理应用进行了优化

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摘要

The benefits of adding explicit DSP operation support to an FPGA-based softcore processor are examined. An experimental DSP processor has been designed, implemented, simulated, and verified on a Xilinx Virtex-5 XC5VSX50T FPGA chip. An initial very simple architecture is upgraded withdifferent supporting hardware to enhance the processor's performance in execution of DSP applications. These hardware enhancement techniques include a specialist execution unit, modification to the memory architecture, adding an extra address control unit, upgrading with more active addressingmodes, and extending the instruction set with zero-overhead looping support. These enhancements reduce the number of instructions used in the inner loop of convolution-based DSP algorithms to a single instruction. By using these proposed enhancement techniques, the overall performance wasimproved by an average of 9 times (800% improvement) in FIR Filter and Matrix Multiplication benchmark DSP applications. The overall area increased by about 1.41 times (41% extra cost). Using in-built DSP blocks in the FPGA instead of logic blocks to implement the arithmetic unit of the processorreduced the power consumption by 14% from 840 mW to 725 mW.
机译：研究了在基于FPGA的软核处理器上添加显式DSP操作支持的好处。在Xilinx Virtex-5 XC5VSX50T FPGA芯片上设计、实现、仿真和验证了一个实验性DSP处理器。最初非常简单的体系结构通过不同的支持硬件进行升级，以提高处理器在执行DSP应用程序时的性能。这些硬件增强技术包括一个专门的执行单元、修改内存体系结构、添加一个额外的地址控制单元、使用更活跃的寻址模式升级，以及使用零开销循环支持扩展指令集。这些增强功能将基于卷积的DSP算法的内环中使用的指令数减少为一条指令。通过使用这些建议的增强技术，FIR滤波器和矩阵乘法基准DSP应用的总体性能平均提高了9倍（800%的改善）。总面积增加了约1.41倍（额外成本为41%）。在FPGA中使用内置DSP模块代替逻辑模块来实现处理器的运算单元，将功耗从840MW降低到725MW，降低了14%。

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