Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

Tohidian M.; Madadi I.; Staszewski R.B.

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Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

机译：Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

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In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm 2 .

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《IEEE Journal of Solid-State Circuits》 |2014年第11期|2575-2587|共13页
作者
Tohidian M.; Madadi I.; Staszewski R.B.;
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作者单位

Electronics Research Laboratory/DIMES, Delft University of Technology, Delft, The Netherlands;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Capacitors; Clocks; Equations; History; Linearity; Noise; Transfer functions; CMOS; IIR; digital equalization; discrete time; high linearity; high order; low noise; low power; low-pass filter; passive; real pole; reconfigurable; switched capacitor;

Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter

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