Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 formula formulatype='inline'tex Notation='TeX'$mu$/tex/formulam HV-CMOS Technology

Moghe Y.Lehmann T.Piessens T.

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Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 formula formulatype='inline'tex Notation='TeX'$mu$/tex/formulam HV-CMOS Technology

机译：Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 formula formulatype="inline"tex Notation="TeX"$mu$/tex/formulam HV-CMOS Technology

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摘要

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5–10 typically and 30–190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20–80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 $mu{hbox {m}}$ high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

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来源
《IEEE Journal of Solid-State Circuits》 |2011年第2期|485-497|共13页
作者
Moghe Y.Lehmann T.Piessens T.;
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作者单位

Silanna Group, Australia;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类
关键词
CMOS; DMOS; HV; HV CMOS; HV-CMOS; HVCMOS; fast; floating; high speed; high voltage; high-speed; high-voltage; level shifter; level-shifter; low power; low-power; reduced area; ultra fast; ultra-fast;

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 formula formulatype='inline'tex Notation='TeX'$mu$/tex/formulam HV-CMOS Technology

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