An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

Hashida T.; Nagata M.

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An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

机译：An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

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摘要

An on-chip waveform capturer exhibits 8.8-bit effective accuracy at a 5-ps timing resolution and 190 $mu$ V voltage, with an effective bandwidth of 700 MHz in a 65-nm CMOS prototype. Voltage by a digital-to-analog converter with selectable slopes and offsets is linearly translated into timing, that is used for strobing a waveform. Programmable timing and voltage generation as well as selective input channels are intended for exhaustive power noise measurements on power delivery networks (PDNs) across rail-to-rail voltage domains in a chip. The measurement procedures are totally governed by an embedded controller. The waveform capturer, in combination with a PDN exciter, realizes in situ derivation of resonance parameters by assembling oscillatory waveforms. A power noise reduction of more than 50% is accomplished through on-chip PDN diagnosis, in which the operation frequencies are selected such that the periodical appearance of PDN resonance is prevented.

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来源
《IEEE Journal of Solid-State Circuits》 |2011年第4期|789-796|共8页
作者
Hashida T.; Nagata M.;
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作者单位

Graduate school of system informatics, Kobe University, Rokkodai-cho, Kobe, Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
On-chip diagnosis; on-chip monitoring; power integrity; power supply noise;

An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration

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