Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

Yeh C.-T.

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Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

机译：电源轨ESD箝位电路的无电容设计，具有可调的保持电压，用于片上ESD保护

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The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.

机译：采用大场效应晶体管（BigFET）布局的n沟道金属氧化物半导体（NMOS）晶体管的基于RC的电源轨ESD钳位电路，有效增强了CMOS IC的ESD鲁棒性。在这项工作中，提出了一种不使用电容器的新型ESD瞬态检测电路，并在65 nm 1.2 V CMOS工艺中进行了验证。与传统的基于RC的ESD瞬态检测电路相比，新型ESD瞬态检测电路的布局面积可以大大减少54%以上。从实验结果来看，新提出的保持电压可调的ESD瞬态检测电路在ESD应力条件下可以实现足够长的导通持续时间，并且在快速上电和瞬态噪声条件下具有更好的抗误触发和瞬态诱导闩锁事件的能力。

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《IEEE Journal of Solid-State Circuits》 |2010年第11期|共11页
作者
Yeh C.-T.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类 NULL;
关键词
Big field-effect transistor (BigFET); electrostatic discharge (ESD); holding voltage; power-rail ESD clamp circuit;

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1. On-Chip ESD Protection Design With Substrate-Triggered Technique for Mixed-Voltage I/O Circuits in Subquarter-Micrometer CMOS Process [J] . Ming-Dou Ker, Kun-Hsien Lin, Chien-Hui Chuang IEEE Transactions on Electron Devices . 2004,第10期

机译：On-Chip ESD Protection Design With Substrate-Triggered Technique for Mixed-Voltage I/O Circuits in Subquarter-Micrometer CMOS Process
2. Design of 2 VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology [J] . {Missing} IEEE Transactions on Electron Devices . 2010,第6期

机译：Design of 2 VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
3. Design of 2formula formulatype="inline" img src="/images/tex/326.gif" alt="times" /formulaVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology [J] . IEEE Transactions on Electron Devices . 2010,第6期

机译：Design of 2formula formulatype="inline" img src="/images/tex/326.gif" alt="times" /formulaVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
4. Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process [C] . Altolaguirre Federico A., Ker Ming-Dou IEEE International Midwest Symposium on Circuits and Systems . 2014

机译：Power-Rail ESD钳位电路，带有嵌入式触发SCR设备，在65-NM CMOS过程中
5. ESD Diode Protection Incorporated on Leadframe Package [O] . Frederick Ray I. Gomez, Edwin M. Graycochea Jr., Nerie R. Gomez, 2020

机译：ESD Diode Protection并列在引线框架上

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

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