An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $mu$m CMOS

Xiang B.; Bao D.; Huang S.Zeng X.

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An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $mu$m CMOS

机译：An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $mu$m CMOS

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摘要

This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row interleaving, nonzero sub-matrix reordering, sum memory quad-partition and read-write bypass, the decoder continuously scans nonzero sub-matrices two by two in the block row-wise order without any memory access conflict. Two phases are fully overlapped with each other, and the check node updating phase always takes the latest sums from the previous variable node updating phase. The sum memory stores not only the posterior sums but also the prior messages, which saves 11,520 memory bits. It only takes 48–54 clock cycles for the decoder to finish one iteration. The read-write accesses to sum memories are reduced by 24.3%–48.8%. Fabricated in the SMIC 0.13 $mu$ m CMOS process, the decoder occupies 4.84 mm $^{2}$ with core area of 3.03 mm$^{2}$, attains 847–955 Mb/s at 214 MHz and 10 iterations, and consumes 342–397 mW at 1.2 V with power efficiency of 39–46 pJ per bit per iteration.

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来源
《IEEE Journal of Solid-State Circuits》 |2011年第6期|1416-1432|共17页
作者
Xiang B.; Bao D.; Huang S.Zeng X.;
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作者单位

State Key Lab. of ASIC and System, Fudan University, Shanghai, China;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
Block column and row interleaving; QC-LDPC codes; decoder architecture; dual-path; fully-overlapped; nonzero sub-matrix reordering; read-write bypass; symmetrical six-stage pipelining;

An 847–955 Mb/s 342–397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 $mu$m CMOS

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