Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

Chi-Hsiang Huang; Yidong Chen; Xun SunArindam MandalVenkata Rajesh PamulaNasser KurdVisvesh S. Sathe

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Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

机译：Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

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Single-inductor multiple-output (SIMO) voltage regulators allow multiple voltage domains to share a single inductor, thus representing a domain-scalable approach to energy-efficient integrated voltage regulation (IVR). However, poor transient response and significant supply voltage ( ${V_{{mathrm {dd}}}}$ ) ripple in SIMO regulators induce severe voltage margins. This article quantifies the prohibitive energy-efficiency impact of these margins and proposes two techniques to address them: dynamic droop allocation (DDA) through concurrent domain- ${V_{{mathrm {dd}}}}$ control and adaptive clocking using the UniCap architecture. We demonstrate the effectiveness of both techniques on an integrated four-domain SIMO system on chip (SoC) in 65-nm CMOS. Measurements indicate that, compared to conventional SIMO implementations, ${V_{{mathrm {dd}}}}$ guardband reductions obtained by UniCaP (98%) and DDA (40%) reduce total system power draw by 53% and 31% respectively.

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《IEEE Journal of Solid-State Circuits》 |2022年第1期|90-102|共13页
作者
Chi-Hsiang Huang; Yidong Chen; Xun SunArindam MandalVenkata Rajesh PamulaNasser KurdVisvesh S. Sathe;
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作者单位

University of Washington, Seattle, WA, USA;

Intel Corporation, Hillsboro, OR, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
Loading; Voltage control; Inductors; Regulators; Transient analysis; Computer architecture; Clocks;

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control

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