A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

Kang Shinwon; Thyagarajan Siva V.; Niknejad Ali M.

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A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

机译：A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

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摘要

In this paper, a 240 GHz 16 Gbps QPSK transmitter is demonstrated in 65 nm bulk CMOS process. The transmitter chain employs an 80 GHz local oscillator and a modulator to generate the data that is amplified by a class-E switching power amplifier. The amplified signal then drives the 240 GHz tripler to generate the required modulated data. By using on-chip slotted loop antennas, the transmitter achieves an EIRP of 1 dBm. A maximum data rate of 16 Gbps is achieved with a transmitter efficiency of 14 pJ/bit.

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来源
《IEEE Journal of Solid-State Circuits》 |2015年第10期|2268-2280|共13页
作者
Kang Shinwon; Thyagarajan Siva V.; Niknejad Ali M.;
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作者单位

Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
architecture; BPSK; class-E power amplifier; communication system; differential hybrid; energy efficiency; frequency tripler; high data rate; modulator; on-chip slotted loop antenna; PRBS generator; QPSK; sub-millimeter-wave; sub-terahertz; transmitter; wideband; 240 GHz; 80 GHz LO;

A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS

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