An 11 GS/s 1.1 GHz Bandwidth Interleaved Delta Sigma DAC for 60 GHz Radio in 65 nm CMOS

Bhide Ameya; Alyandpour Atila

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An 11 GS/s 1.1 GHz Bandwidth Interleaved Delta Sigma DAC for 60 GHz Radio in 65 nm CMOS

机译：An 11 GS/s 1.1 GHz Bandwidth Interleaved Delta Sigma DAC for 60 GHz Radio in 65 nm CMOS

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摘要

This work presents an 11 GS/s 1.1 GHz bandwidth interleaved Delta Sigma DAC in 65 nm CMOS for the 60 GHz radio baseband. The high sample rate is achieved by using a two-channel interleaved MASH 1-1 architecture with a 4 bit output resulting in a predominantly digital DAC with only 15 analog current cells. Two-channel interleaving allows the use of a single clock for the logic and the multiplexing which requires each channel to operate at half sampling rate of 5.5 GHz. To enable this, a look-ahead technique is proposed that decouples the two channels within the integrator feedback path thereby improving the speed as compared to conventional loop-unrolling. Measurement results show that the Delta Sigma DAC achieves a 53 dB SFDR, -49 dBc IM3 and 39 dB SNDR within a 1.1 GHz bandwidth while consuming 117 mW from 1 V digital/1.2 V analog supplies. Furthermore, the proposed Delta Sigma DAC can satisfy the spectral mask of the IEEE 802.11 had WiGig standard with a second order reconstruction filter.

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来源
《IEEE Journal of Solid-State Circuits》 |2015年第10期|2306-2318|共13页
作者
Bhide Ameya; Alyandpour Atila;
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作者单位

Linkoping Univ, Dept Elect Engn, Div Integrated Circuits & Syst, SE-58183 Linkoping, Sweden;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类基本电子电路;
关键词
High speed; IEEE 80211ad; MASH; Delta Sigma DAC; time-interleaving; WiGig; 60 GHz radio;

An 11 GS/s 1.1 GHz Bandwidth Interleaved Delta Sigma DAC for 60 GHz Radio in 65 nm CMOS

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