POWER7#x2122;, a Highly Parallel, Scalable Multi-Core High End Server Processor

Wendel D. F.; Kalla R.; Warnock J.Cargnoni R.Chu S. G.Clabes J. G.Dreps D.Hrusecky D.Friedrich J.Islam S.Kahle J.Leenstra J.Mittal G.Paredes J.Pille J.Restle P. J.Sinharoy B.Smith G.Starke W. J.Taylor S.Van Norstrand A. J.Weitzel S.Williams P. G.Zyuban V.

首页> 外文期刊>IEEE Journal of Solid-State Circuits >POWER7#x2122;, a Highly Parallel, Scalable Multi-Core High End Server Processor

【24h】

POWER7#x2122;, a Highly Parallel, Scalable Multi-Core High End Server Processor

机译：POWER7#x2122;, a Highly Parallel, Scalable Multi-Core High End Server Processor

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相关主题

摘要

This paper gives an overview of the latest member of the POWER™ processor family, POWER7™. Eight quad-threaded cores, operating at frequencies up to 4.14 GHz, are integrated together with two memory controllers and high speed system links on a 567 mm$^{2}$ die, employing 1.2B transistors in a 45 $~$nm CMOS SOI technology with 11 layers of low-k copper wiring. The technology features deep trench capacitors which are used to build a 32 MB embedded DRAM L3 based on a 0.067 $mu$m$^{2}$ DRAM cell. The functionally equivalent chip transistor count would have been over 2.7B if the L3 had been implemented with a conventional 6 transistor SRAM cell. (A detailed paper about the eDRAM implementation will be given in a separate paper of this Journal). Deep trench capacitors are also used to reduce on-chip voltage island supply noise. This paper describes the organization of the design and the features of the processor core, before moving on to discuss the circuits used for analog elements, clock generation and distribution, and I/O designs. The final section describes the details of the clocked storage elements, including special features for test, debug, and chip frequency tuning.

著录项

来源
《IEEE Journal of Solid-State Circuits》 |2011年第1期|145-161|共17页
作者
Wendel D. F.; Kalla R.; Warnock J.Cargnoni R.Chu S. G.Clabes J. G.Dreps D.Hrusecky D.Friedrich J.Islam S.Kahle J.Leenstra J.Mittal G.Paredes J.Pille J.Restle P. J.Sinharoy B.Smith G.Starke W. J.Taylor S.Van Norstrand A. J.Weitzel S.Williams P. G.Zyuban V.;
展开▼
作者单位

IBM Research & Development GmbH, Boeblingen, Germany;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
中图分类
关键词
CML circuits; debug features; Clocked storage element design; L3 cache; LBIST; POWER processor; POWER7; SER; SEU; SMP; SOI; clock grid; deep trench capacitor; design for reliability; design for test; differential I/O; digital PLL; duty cycle correction; eight core processor; embedded DRAM; flip-flop design; high-speed I/O; latch; microprocessor; multi-core; multiport SRAM; pulsed-clock latch; quad-threaded core; vector register file; vector scalar unit;

POWER7#x2122;, a Highly Parallel, Scalable Multi-Core High End Server Processor

摘要

著录项

相关主题

期刊订阅