A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

Shiga H.

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A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

机译：A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

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摘要

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ?±220 mV is achieved even with the small cell size of 0.252 ??m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

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来源
《IEEE Journal of Solid-State Circuits》 |2010年第1期|共11页
作者
Shiga H.;
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作者单位

Toshiba Corp. Semicond. Co., Yokohama, Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种英语
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关键词
CMOS digital integrated circuits; DRAM chips; CMOS process; DDR2 FeRAM memory cell; SDRAM compatible DDR2 interface; bandwidth 400 MHz; bit rate 1.6 Gbit/s; capacitance 100 fF to 60 fF; ferroelectric random access memory; parasitic capacitance sensing scheme; scalable octal bitline architecture; size 130 nm; time 2 ns; voltage -220 mV; voltage 220 mV; voltage 50 mV; FeRAM; RAM; ferroelectric memory; nonvolatile memory; random access memory;

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

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